Peaking network techniques have been implemented in integrated circuit devices to extend the bandwidth of high speed inputs/outputs (IOs) to accommodate the ever increasing interconnect signal frequencies. In a peaking network, an inductor is added in series with a termination resistance to extend the frequency response of the IO. The termination resistance is typically implemented with a poly resistor in the integrated circuit device. However, over different manufacturing process, operating voltage, and operating temperature corners, there can be wide variations in the termination resistance due to variations in the poly sheet resistance over these corners.
To counter variations of the termination resistance over process and operating corners and to provide greater flexibility in the DC matching of the IO at the circuit board level, a programmable termination resistance circuit is used. The programmable termination resistance circuit allows the selection of different banks of poly resistors to be coupled together to yield a range of possible resistance depending on how the circuit is programmed. The range of resistance provided by the programmable termination resistance circuit allows each individual integrated circuit device to be custom programmed to provide a more accurate termination resistance. The custom programming depends on the particular operating conditions of that device in a particular design application, and depends on the particular process corner that the device was subjected to during manufacturing. However, while the programmable termination resistance circuit provides a more accurate termination resistance, the different selection of the different banks of poly resistors due to the different custom programming from device to device results in variations of the parasitic capacitance of the programmable termination resistance circuit. Variations in the parasitic capacitance can cause degradation of signal integrity due to undesirable ringing and increase of settling time of a signal.